Regviz

Espressif Systems /ESP32-S3 /SPI1 /FLASH_WAITI_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FLASH_WAITI_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/SPI1/FLASH_WAITI_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WAITI_EN)WAITI_EN 0 (WAITI_DUMMY)WAITI_DUMMY 0WAITI_CMD0WAITI_DUMMY_CYCLELEN

Description

SPI1 wait idle control register

Fields

WAITI_EN

Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.
WAITI_DUMMY

Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).
WAITI_CMD

The command value of auto wait flash idle transfer(RDSR).
WAITI_DUMMY_CYCLELEN

The dummy cycle length when wait flash idle(RDSR).

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data